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Topology: NHLT: Intel: SSP: Handle differences for ACE3.x
authorSeppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
Wed, 17 Jul 2024 16:09:12 +0000 (19:09 +0300)
committerJaroslav Kysela <perex@perex.cz>
Wed, 23 Oct 2024 11:01:07 +0000 (13:01 +0200)
commit0c780e1fa02b9d4900fb6cc79b748628fe33bd48
tree94e66cde82cd4c726eb5668ca4cc4dbc21aaaddftree | snapshot
parentbd968a3f411850c489958c5315e72189f3c68208commit | diff
Topology: NHLT: Intel: SSP: Handle differences for ACE3.x

- The SSC1 bits 21 and 20, TSRE and RSRE, do not exist.
- The SSC0 bit 30 ACS does not exist.
- The SSC0 bit 6 ECS does not exist but needs to be set, add note.
- The MDIVXCTRL bits 20:21 MNDSS does not exist.

Closes: https://github.com/alsa-project/alsa-utils/pull/276
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
topology/nhlt/intel/ssp/ssp-process.c diff | blob | history
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